Date: 5 Dec 2019 (Thursday)
Time: 09:30-17:00
Venue: CKK Auditorium, Hong Kong Science Park
Organiser: HKSTP & UMEC
Co-organiser: CUHK, HKU, HKUST, IEEE EDS
Supporting organiser: HKSAIR, HKAI LAB, NeuHelium
由香港科技園和聯(lián)合微電子中心聯(lián)合主辦的 HKSTP Thought-leadership Series：2019 AI 芯片峰會將討論與 AI 芯片開發(fā)相關(guān)的各種主題，包括設(shè)計(jì)工具的最新發(fā)展與異質(zhì)結(jié)構(gòu)整合技術(shù)的趨勢，以及市場的未來方向。
日期: 2019 年 12 月 5 日（星期四）
時(shí)間: 09:30-17:00
地點(diǎn): 香港科學(xué)園CKK高錕會議中心 (金蛋)
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活動背景
Looking forward the 5G, V2X and Smart City, AI architecture will be blooming not only the upstream cloud computing, but also midstream edge computing. The edge computing AI chips need to be more boosted by upgrading chip design architecture and changing the transistor technology in the front end.
展望5G、車聯(lián)網(wǎng)和智能城市，人工智能架構(gòu)不僅在上游云計(jì)算領(lǐng)域，也在中游的邊緣計(jì)算領(lǐng)域中蓬勃發(fā)展。邊緣計(jì)算的人工智能芯片需要通過升級芯片設(shè)計(jì)架構(gòu)和改變前端的晶體管技術(shù)，來得到更大的發(fā)展。
To address market needs, system packages through heterogeneous integration has taken the driver’s seat and propel system performances toward smart computing, wide data bandwidth, small form factor, with low or zero latency and energy efficiency. And all these are capped by ever better system cost per function as technology and product migrate from generation to generation.
為了滿足市場需求，通過異構(gòu)集成的系統(tǒng)占據(jù)了主導(dǎo)地位，且推動系統(tǒng)性能朝著智能計(jì)算、更寬的數(shù)據(jù)帶寬、小型化設(shè)計(jì)、低/零延遲和能效的方向發(fā)展。隨著技術(shù)和產(chǎn)品一代又一代的遷移，所有這些性能的分項(xiàng)系統(tǒng)成本都將更容易被同時(shí)涵蓋。
Facing the enormous challenges of high design complexity and tight time-to-market, advances design tools (i.e., EDA tools) are critical for timely and competitive design of AI chips. The morning section will introduce novel machine learning based design methodologies and supporting tools to aid and facilitate the design and verification of AI chips and accelerators.
面對設(shè)計(jì)復(fù)雜度高和市場時(shí)間緊湊的巨大挑戰(zhàn)，先進(jìn)的設(shè)計(jì)工具（即EDA工具）對于AI芯片的及時(shí)性及具競爭力的設(shè)計(jì)至關(guān)重要。早上議程將介紹新的基于機(jī)器學(xué)習(xí)的設(shè)計(jì)方法和協(xié)助工具，以幫助及促進(jìn)人工智能芯片和加速器的設(shè)計(jì)及驗(yàn)證。
AI Chips and Systems Workshop, once again gathering top researchers and bright minds to share their treasure experiences on future technology development roadmap, challenges, and effective solutions.
本次人工智能芯片和系統(tǒng)研討會，將再次聚集各界頂尖的研究人員和杰出的人才，分享他們對未來技術(shù)發(fā)展的遠(yuǎn)景、挑戰(zhàn)和有效解決方案的寶貴經(jīng)驗(yàn)。
Dec. 5th, 2019 (Thursday)
Programme Rundown
Time | Rundown |
09:00-09:30 | Registration |
Morning Section : AI-Assisted Design Tool for AI Hardware 人工智能硬件輔助設(shè)計(jì)工具 | |
09:30-09:35 | Opening Remarks - Hong Kong Science and Technology Parks Corporation (HKSTP) |
09:35-09:40 | Opening Remarks - United Microelectronics Centre (UMEC) |
09:40-09:45 | Photo-taking |
09:50-10:15 | Keynote 1: How does new IC design approach enable AI applications? 新的集成電路設(shè)計(jì)方法如何實(shí)現(xiàn)人工智能應(yīng)用？ Dr. Walden Rhines, CEO Emeritus, Mentor |
10:20-10:45 | Keynote 2: Computing with Heterogeneous Hardware Systems for the AI Revolution 面向人工智能革命的異構(gòu)硬件系統(tǒng)計(jì)算 Prof. Deming Chen, University of Illinois Urbana-Champaign |
10:50-11:15 | Keynote 3: AI in Physical Design Tools 物理設(shè)計(jì)工具中的人工智能 Prof. Evangeline Young, Professor, Department of Computer Science and Engineering, CUHK |
11:15-11:30 | Coffee Break |
11:30-11:55 | Keynote 4: Machine Learning for Chip, Package and Board Design 機(jī)器學(xué)習(xí)應(yīng)用于芯片, 封裝與電路板設(shè)計(jì) Prof. Elyse Rosenbaum, University of Illinois Urbana-Champaign |
11:55-12:35 | Panel Discussion: New EDA tools ? Beyond traditional EDA what is a chance for start-ups 新的EDA工具？與傳統(tǒng)的EDA相比, 新創(chuàng)企業(yè)的機(jī)會在哪? Moderator: Dr. Mei Kei Ieong, CEO, UMEC(HK) Panel Members: Dr. Walden Rhines, CEO Emeritus, Mentor Charlie Huang, Former SVP Cadence (TBC) Prof. Deming Chen, University of Illinois Urbana-Champaign Prof. Martin Wong, Dean of Engineering, CUHK |
12:35 | VIP Lunch @ ClubONe HKSTP |
Afternoon Section: Heterogeneous System Integration & Hardware-Aware Design Algorithms | |
14:00-14:20 | AI Chips Centre and Emerging Smart System (ACCESS) overview 人工智能芯片中心與新興智能系統(tǒng)（ACCESS）介紹 Prof. Tim Cheng, Dean of Engineering, |
14:20-14:40 | Keynote 5: Efficient Reconfigurable Hardware for AI 面向人工智能的高效可重構(gòu)硬件 Dr. Hayden So, Department of Electrical and Electronic Engineering, The University of Hong Kong |
14:40-15:00 | Keynote 6: Energy efficient AI accelerators for sensor-based edge devices 用于傳感器邊緣設(shè)備的節(jié)能人工智能加速器 Prof. Chi Ying Tsui, Professor, Department of Electrical and Electronic Engineering |
15:00-15:20 | Coffee Break |
15:20-15:40 | Keynote 7: The Challenge and Opportunity of Heterogeneous System Integration 異構(gòu)系統(tǒng)集成的挑戰(zhàn)與機(jī)遇 Mr. Nelson Fan, VP, APT Business Development, ASM Pacific Technology |
15:40-16:00 | Keynote 8: Discontinuities Drive 3DIC & Chip Integration 不連續(xù)性驅(qū)動3DIC和芯片集成 Dr. Walden Rhines, CEO Emeritus, Mentor |
16:00-16:40 | Panel Discussion: What’s kind of microelectronics infrastructure is needed in Hong Kong ? 香港需要什么樣的微電子基礎(chǔ)設(shè)施？ Moderator: Dr. Mei Kei Ieong, CEO, UMEC(HK) Panel Members: Mr. Nelson Fan, VP, APT Business Development, ASM Pacific Technology Prof. Tim Cheng, Dean of Engineering, |
16:40-16:45 | Closing Remarks Dr. Mei Kei Ieong, CEO, UMEC(HK) |
16:50 | End of Programme |
Dec. 6th, 2019 (Friday)
Programme (by invitation only)
Program | Remark |
SenseTime | The world’s leading artificial intelligence platform company valued above USD 4.5 billion. |
A.I.R – RCC (Artificial Intelligence and Robotics – Robotics Catalysing Centre) | HKSTP newest facility integrating infrastructure, technical support and knowledge exchange for AI and robotics communities |
UMEC (HK)Ltd. | An innovative research & development centre to develop next-generation artificial intelligence chips and 5G applications |
Collaboration discussion | Topic: (1) 3D IC (2) ACCESS (AI Chips Centre and Emerging Smart System) |
End of the programme |
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